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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2006, zarlink semiconductor inc. all rights reserved. features ? meets requirements of gr-253 for sonet stratum 3 and sonet minimum clocks (smc) ? meets requirements of gr-1244 for stratum 3 ? meets requirements of g.813 option 1 and 2 for sdh equipment clocks (sec) ? generates clocks for st-bus, ds1, ds2, ds3, oc-3, e1, e2, e3, stm-1 and 19.44 mhz ? holdover accuracy to 1x10 -12 meets gr-1244 stratum 3e and itu-t g.812 requirements ? continuously monitors primary and secondary reference clocks ? provides ?hit-less? reference switching ? compensates for master clock oscillator accuracy ? detects frequency of both reference clocks and synchronizes to any combination of 8 khz, 1.544 mhz, 2.048 mhz and 19.44 mhz reference frequencies. ? allows hardware or microprocessor control ? pin compatible with mt90401 device. applications ? synchronization for sdh and sonet network elements ? clock generation for st-bus and gci backplanes description the zl30402 is a network element phase-locked loop designed to synchronize sdh and sonet systems. in addition, it gene rates multiple clocks for legacy pdh equipment and provides timing for st-bus and gci backplanes. the zl30402 operates in normal (locked), holdover and free-run modes to ensure that in the presence of jitter, wander and interruptions to the reference signals, the generated clocks meet international standards. the filtering characteristics of the pll are hardware or software selectable and they do not require any external adjustable components. the zl30402 uses an external 20 mhz master clock oscillator to provide a st able timing source for the holdover operation. the zl30402 operates from a single 3.3 v power supply and offers a 5 v tolerant microprocessor interface. may 2006 ordering information zl30402/qcc 80 pin lqfp trays zl30402qcg1 80 pin lqfp* trays, bake & drypack *pb free matte tin -40 c to +85 c zl30402 sonet/sdh network element pll data sheet figure 1 - functional block diagram control state machine mux microport primary acquisition pll ms1 ms2 hw reset sec trst c19o c34/c44 c16o c8o c4o c2o c1.5o f16o f8o pri c6o holdover lock d0-d7 r/w cs c155p/n e3ds3/oc3 f0o secondary acquisition pll refalign ds e3/ds3 jtag ieee 1149.1a master clock frequency calibration apll a0-a6 tms tdo tdi tc l k clock synthesizer core pll refsel fcs c20i vdd gnd
zl30402 data sheet table of contents 2 zarlink semiconductor inc. features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 change summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.0 zl30402 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 acquisition plls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 core pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 clock synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 output clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5 output clocks phase adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6 control state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.1 clock modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.2 zl30402 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.6.3 reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.4 free-run state (free-run mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.5 normal state (normal mode or locked mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6.6 holdover state (holdover mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.7 auto holdover state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.8 state transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.0 master clock frequency calibration circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0 hardware and software control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.1 hardware control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.1 control pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1.2 status pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2 software control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.1 control bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2.2 status bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.3 zl30402 register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.2.4 register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.0 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 zl30402 mode switching - examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1.1 system start-up sequence: free-run --> holdover --> normal . . . . . . . . . . . . . . . . . . . . . 28 5.1.2 single reference operation: no rmal --> auto holdover --> normal . . . . . . . . . . . . . . . . 29 5.1.3 dual reference operation: normal --> auto holdover--> holdover --> normal. . . . . 30 5.1.4 reference switching (refsel): normal --> holdover --> normal . . . . . . . . . . . . . . . . . . . . 31 5.2 programming master clock oscillator freq uency calibration register . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.0 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.1 ac and dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.2 performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
zl30402 data sheet list of figures 3 zarlink semiconductor inc. figure 1 - functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - pin connections for 80-pin lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3 - core pll functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4 - c19o, c155o, c34/c44 clock generation options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 5 - zl30402 state machine. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6 - hardware and software control options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 7 - transition from free-run to normal mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 8 - automatic entry into auto holdover state and eecovery into normal mode . . . . . . . . . . . . . . . . . . . . . 29 figure 9 - entry into auto holdover state and recovery into normal mode by switching references . . . . . . . . . . . 30 figure 10 - manual reference switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 11 - timing parameters measurement voltage levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 12 - microport timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 13 - st-bus and gci output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 14 - ds1, ds2 and c19o clock timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15 - c155o and c19o timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 16 - input reference to output clock phase alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 17 - input control signal setup and hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 18 - e3 and ds3 output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
zl30402 data sheet list of tables 4 zarlink semiconductor inc. table 1 - operating modes and states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 2 - filter characteristic selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 3 - reference source select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4 - zl30402 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 5 - control register 1 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6 - status register 1 (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7 - control register 2 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 8 - phase offset register 2 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 9 - phase offset register 1 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 10 - device id register (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11 - control register 3 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12 - clock disable register 1 (r/w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 13 - clock disable register 2 (r/w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 14 - core pll control register (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 15 - fine phase offset register (r/w). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 16 - primary acquisition pll status register (r). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 17 - secondary acquisition pll status register (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 18 - master clock frequency calibration register 4 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 19 - master clock frequency calibration register 3 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 20 - master clock frequency calibration register 2 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 21 - master clock frequency calibration register 1 (r/w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
zl30402 data sheet 5 zarlink semiconductor inc. change summary the following table captures the changes from the april 2005 issue. page item change 1 updated ordering information.
zl30402 data sheet 6 zarlink semiconductor inc. 1.0 zl30402 pinout 1.1 pin connections figure 2 - pin connections for 80-pin lqfp package zl30402 40 42 44 46 48 50 52 54 56 58 60 22 24 26 28 30 34 36 38 32 62 80 78 76 74 72 68 66 64 70 20 18 16 14 12 10 8 6 4 2 tdi tc l k tms tdo nc gnd pri sec e3/ds3 e3ds3/oc3 c155p c155n vdd avdd gnd ic gnd nc trst nc ms1 a2 a1 c4o c8o c16o f16o gnd vdd fcs a5 f0o c2o ic a3 a4 ms2 gnd a6 f8o ic oe cs reset hw d1 d2 d3 gnd ic d6 r/w ic vdd d4 d5 d7 ic a0 c1.5o c19o refsel refalign vdd nc c20i c34/c44 gnd vdd holdover nc lock nc ds ic ic gnd ic c6o d0
zl30402 data sheet 7 zarlink semiconductor inc. pin description pin # name description 1ic internal connection . leave unconnected. 2-5 a1-a4 address 1 to 4 (5 v tolerant input). address i nputs for the parallel processor interface. connect to ground in hardware control. 6gnd ground . negative power supply. 7-8 a5-a6 address 5 to 6 (5 v tolerant input). address i nputs for the parallel processor interface. connect to ground in hardware control. 9fcs filter characteristi c select (input) . in hardware control, fcs selects the filtering characterist ics of the zl30402. set this pin high to have a loop filter corner frequency of 0.1 hz and limit the phase slope to 885 ns per second. set this pin low to have corner frequency of 1.1 hz and limit the phase slope to 41 ns per 1.326 ms. connect to ground in software control. this pin is internally pulled down to gnd. 10 vdd positive power supply. 11 gnd ground . 12 f16o frame pulse st-bus 8.192 mb/s (cmos tristate output). this is an 8 khz, 61 ns wide, active low framing pulse, which marks beginning of a st-bus frame. this frame pulse is typically used for st-bus operation at 8.192 mb/s 13 c16o clock 16.384 mhz (cmos tristate output). this clock is used for st-bus operation at 8.192 mb/s. 14 c8o clock 8.192 mhz (cmos tristate output). this clock is used for st-bus operation at 8.192 mb/s. 15 c4o clock 4.096 mhz (cmos tristate output). this clock is used for st-bus operation at 2.048 mb/s. 16 c2o clock 2.048 mhz (cmos tristate output). this clock is used for st-bus operation at 2.048 mb/s. 17 f0o frame pulse st-bus 2.048 mb/s (cmos tristate output). this is an 8 khz, 244 ns, active low framing pulse, which marks the beginning of a st-bus frame. this is typically used for st-bus operation at 2.048 mb/s and 4.096 mb/s. 18 ms1 mode select 1 (input). the ms1 and ms2 pins select the zl30402 mode of operation (normal, holdover or free-r un), see table 1 on page 18 for details. the logic level at this input is sampled by the rising edge of the f8o frame pulse. connect to ground in software control. 19 ms2 mode select 2 (input). the ms2 and ms1 pins select the zl30402 mode of operation (normal, holdover or free-r un), see table 1 on page 18 for details. the logic level at this input is sampled by the rising edge of the f8o frame pulse. connect to ground in software control.
zl30402 data sheet 8 zarlink semiconductor inc. 20 f8o frame pulse st-bus/gci 8.192 mb/s (cmos tristate output). this is an 8 khz, 122 ns, active high framing pulse , which marks the beginning of a st- bus/gci frame. this is typically used for st-bus/gci operation at 8.192 mb/s. see figure 13 for details. 21 e3ds3/oc3 e3ds3 or oc3 selection (input). in hardware control, a logic low on this pin enables the c155p/n outputs (pin 30 a nd pin 31) and sets the c34/c44 output (pin 53) to provide c8 or c11 clocks. l ogic high at this input disables the c155 clock outputs (high impedance) and sets c34/c44 output to provide c34 and c44 clocks. in software control connect this pin to ground. 22 e3/ds3 e3 or ds3 selection (input). in hardware control, when the e3ds3/oc3 pin is set high, logic low on e3/ds3 pin selects a 44.736 mhz clock on c34/c44 output and logic high selects 34.368 mhz clock. when e3ds3/oc3 pin is set low, logic low on e3/ds3 pin selects 11.184 mhz clock on c34/c44 output and logic high selects 8.592 mhz clock. connect this input to ground in software control. 23 sec secondary reference (input). this input is us ed as a secondary reference source for synchronization. the zl30402 can synchronize to the falling edge of the 8 khz, 1.544 mhz or 2.048 mhz clocks and the rising edge of the 19.44 mhz clock. in hardware control, selection of the input reference is based upon the refsel control input. this pin is internally pulled up to vdd. 24 pri primary reference (input). this input is used as a primary reference source for synchronization. the zl30402 can sync hronize to the falling edge of the 8 khz, 1.544 mhz or 2.048 mhz clocks and the rising edge of the 19.44 mhz clock. in hardware control, selection of the input reference is based upon the refsel control input. this pin is internally pulled up to vdd. 25 gnd ground . 26 ic internal connection . leave unconnected. 27 gnd ground . 28 avdd positive analog power supply . connect this pin to vdd. 29 vdd positive power supply . 30 31 c155n c155p clock 155.52 mhz (lvds output). differential out puts for a 155.52 mhz clock. these outputs are enabled by applying logic low to e3ds3/oc3 input or they can be switched into high impedance state by applying logic high. 32 gnd ground . 33 nc no internal bonding connection . leave unconnected. 34 tdo ieee1149.1a test data output (cmos output). jtag serial data is output on this pin on the falling edge of tclk clock. if not used, this pin should be left unconnected. pin description (continued) pin # name description
zl30402 data sheet 9 zarlink semiconductor inc. 35 tms ieee1149.1a test mode selection (3.3 v input). jtag si gnal that controls the state transition on the tap controller. this pin is internally pulled up to vdd. if not used, this pin should be left unconnected. 36 tclk ieee1149.1a test clock signal (5.5 v tolerant input). input clock for the jtag test logic. if not used, this pin should be pulled up to vdd. 37 trst ieee1149.1a reset signal (3.3 v input). asynchronous reset for the jtag tap controller. this pin should be pulsed low on power-up to ensure that the device in the normal functional state. this pin is internally pulled up to vdd. if not used, this pin should be connected to gnd. 38 tdi ieee1149.1a test data input (3.3 v input). input for jtag serial test instructions and data. this pin is inter nally pulled up to vdd. if not used, this pin should be left unconnected. 39 nc no internal bonding connection. leave unconnected. 40 nc no internal bonding connection. leave unconnected. 41 ic internal connection. leave unconnected. 42 c1.5o clock 1.544 mhz (cmos tristate output). this output provides a 1.544 mhz ds1 rate clock. 43 c6o clock 6.312 mhz (cmos tristate output). this output provides a 6.312 mhz ds2 rate clock. 44 ic internal connection . connect this pin to ground. 45 gnd ground . 46 c19o clock 19.44 mhz (cmos tristate output). this output provides a 19.44 mhz clock. 47 refsel reference source select (input). a logic low selects the pri (primary) reference source as the input refer ence signal and logic high selects the sec (secondary) input. the logic level at this input is sampled at the rising edge of f8o. this pin is internally pulled down to gnd. 48 refalign reference align (input). in hardware control a high to low transition at this input initiates phase realignment between the input reference and the generated output clocks. this pin is internally pulled down to gnd. 49 vdd positive power supply . 50 nc no internal bonding connection. leave unconnected. 51 c20i clock 20 mhz (5.5 v tolerant input). this pin is the input for the 20 mhz master clock oscillator. 52 gnd digital ground . pin description (continued) pin # name description
zl30402 data sheet 10 zarlink semiconductor inc. 53 c34/c44 clock 34.368 mhz / clock 44.736 mhz (cmos output). this clock is programmable to be either 34.368 mhz (for e3 applications) or 44.736 mhz (for ds3 applications) when e3ds3/oc3 is high, or to be either 8.592mhz or 11.184 mhz when e3ds3/oc3 is low. see description of e3ds3/oc3 and e3/ds3 inputs for details. in software control the functionality of this output is controlled by control register 2 (table 7 "control register 2 (r/w)"). 54 vdd positive power supply . 55 holdover holdover indicator (cmos output). logic high at this output indi cates that the device is in holdover mode. 56 nc no internal bonding connection . leave unconnected. 57 lock lock indicator (cmos output). logic high at this output indicates that zl30402 is locked to the input reference. 58 nc no internal bonding connection. leave unconnected. 59 ds data strobe (5 v tolerant input). this input is the active low data strobe of the processor interface. 60 ic internal connection . connect to ground. 61 ic internal connection. leave unconnected. 62 oe output enable (input). logic high on this input enables c19, f16 , c16 , c8, c6, c4 , c2, c1.5, f8 and f0 signals. pulling this inpu t low will force the output clocks pins into a high impedance state. 63 cs chip select (5 v tolerant input). this active low input enables the microprocessor interface. when cs is set to high, the microprocessor interface is idle and all data bus i/o pins will be in a high impedance state. 64 reset reset (5 v tolerant input). this active low input forces the zl30402 into a reset state. the reset pin must be held low for a minimum of 1s to reset the device properly. the zl30402 must be reset after power-up. 65 hw hardware/software control (input). if this pin it tied low, the zl30402 is controlled via the microport. if it is tied high, the zl30402 is controlled via the control pins ms1, ms2, fcs, refsel, refalign , e3/ds3 and e3ds3/oc3 . 66-69 d0 - d3 data 0 to data 3 (5 v tolerant three-state i/o). these signals combined with d4 - d7 form the bi-directional data bus of the microprocessor interface (d0 is the least significant bit). 70 gnd ground . 71 ic internal connection (input). connect this pin to ground. 72 ic internal connection (input). connect this pin to ground. 73 vdd positive power supply . pin description (continued) pin # name description
zl30402 data sheet 11 zarlink semiconductor inc. 2.0 functional description the zl30402 is a network element pll designed to prov ide timing for sdh and sonet equipment conforming to itu-t, ansi, etsi and telcordia recommendations. in addition, it genera tes clocks for legacy pdh equipment operating at ds1, ds2, ds3, e1, and e3 rates. the zl 30402 provides clocks for industry standard st-bus and gci backplanes, and it also supports h.110 timing requ irements. the functional bloc k diagram of the zl30402 is shown in figure 1 "functional block diagram" and it s operation is described in the following section. 2.1 acquisition plls the zl30402 has two acquisition plls for monitoring availab ility and quality of the pr imary (pri) and secondary (sec) reference clocks. each acquisition pll operates independently and locks to the falling edges of one of the three input reference frequencies: 8 khz, 1.544 mhz, 2.048 m hz or to the rising edge of 19.44 mhz. the reference frequency can be determined from reading the acquisition p ll status register bits inpfreq1 and inpfreq0 (see table 16 "primary acquisition pll status register (r)" and table 17 "secondary acquis ition pll status register (r)"). the primary and secondary acquisition plls are designed to pr ovide status information that identifies two levels of reference clock quality. for clarity, only the primary acquisi tion pll is referenced in the text, but the same applies to the secondary acquisition pll. - reference frequency drifts more than 30000 ppm or is lo st completely. in response, the primary acquisition pll enters its own holdover mode and indicates this by asserting the holdover bit in the primary acquisition pll status register (table 16 "primary acquis ition pll status register (r )"). entry into holdover forces the core pll into the auto holdover state. - reference frequency drifts more than 104 ppm. in re sponse the primary acquisition pll asserts the frequency limit bit pafl in its prim ary acquisition pll status register (table 16) indicating that the reference frequency crossed the boundary of the capture range. outputs of both acquisition plls are connected to a mult iplexer (mux), which allows selecting a reference signal that guarantees better traceability to the primary referenc e clock. this multiplexer channels binary words to the core pll digital phase detector (instead of analog signal s). application of the digita l phase detector in the core pll eliminates quantization errors and improves phase alignment accuracy. the bandwidth of the acquisition pll is much wider than t he bandwidth of the following core pll. this feature allows cascading acquisition and core plls withou t changing the transfer function of the core pll. 74 - 77 d4 - d7 data 4 to data 7 (5 v tolerant three-state i/o) . these signals combine with d0 - d3 form the bi-directional data bus of the processor interface (d7 is the most significant bit). 78 r/w read/write strobe (5 v tolerant input). this input controls the direction of the data bus d[0-7] during a mi croprocessor access. when r/w is high, the parallel processor is reading data from the zl30402. when low, the parallel processor is writing data to the zl30402. 79 a0 address 0 (5 v tolerant input). address input for the microprocessor interface. a0 is the least significant input. 80 ic internal connection (input). connect this pin to ground. pin description (continued) pin # name description
zl30402 data sheet 12 zarlink semiconductor inc. 2.2 core pll the most critical element of the zl30402 is its core pll, which generates a phase-locked clock, filters jitter and wander and suppresses input phase transients. all of these features are in agreement wi th international standards: - g.813 option 1 and 2 clocks for sdh equipment - gr-253 for sonet stratum 3 and sonet minimum clocks (smc) - gr-1244 for stratum 3 clocks the core pll supports three mandatory modes of operat ion: free-run, normal (locked) and holdover. each of these modes places specific requirements on the building blocks of the core pll. - in free-run mode, the core pll locks to the 20 mhz master cloc k oscillator connected to pin c20i. the stability of the generated clo ck remains the same as the stability of t he master clock osci llator but frequency accuracy is greatly improved by the master clock freq uency calibration register. this register compensates oscillator frequency, practically elim inating manufacturing tolerances. - in normal mode, the core pll locks to one of the acquisition plls. both acquisition plls provide preprocessed phase data to the core pll including detec tion of reference clock qual ity. this preprocessing reduces the load on the core pll and improves quality of the generated clock. - in holdover mode, the core pll generates a clock based on data collected from past reference signals. the core pll enters holdover mode if the attached acquisition pll switches into the holdover state or under external software or hardware control. some of the key elements of the core pll are show n in figure 3 "core pll functional block diagram". figure 3 - core pll functional block diagram digitally controlled oscillator (dco) : the dco is an arithmetic unit t hat continuously generates a stream of numbers that represent the phase-lo cked clock. these numbers are passed to the clock synthesizer (see section 2.3) where they are conv erted into electrical clock si gnals of different frequencies. filters : in normal mode, the clock generated by the dco is phase-locked to the input reference signal and band- limited to meet network synchronization standards. th e zl30402 provides two software programmable (control reg 1) and two hardware selectable (fcs pin) filtering opti ons. the filtering characteristics are similar to a first order low pass filter with corner fre quencies that support international standards: - 0.1 hz filter: supports g.813 option 2 clock, gr-253 so net stratum 3 and gr-253 sonet minimum clock - 1.1 hz filter: supports g.813 option 1 and gr-1244 stratum 3 clock fsm dco filters phase detector mux lock refalign fcs
zl30402 data sheet 13 zarlink semiconductor inc. lock indicator : entry into normal mode is flagged by the lock status bit or pin. lo ck is declared when the acquisition pll is locked to the reference clock and the core pll is locked to the acquisition pll. frequency lock means that the center frequency of the pll is identical to the reference frequency and phase error excursions caused by jitter and wander are symmetrical around some long-term phase error average. reference re-alignment : reference realignment is performed to erase a residual phase error that has been accumulated between the reference and output clocks as a re sult of reference switching. a high to low transition on the refalign pin (or bit) initiates phase realignment with a phase slope on the output clocks limited to 41 ns in 1.326 ms for the 1.1 hz filter and to 885 ns in 1 s for 0.1 hz filter. please refer to the zlan-27 "phase alignment between 8 khz output and 8 khz input reference on zl30402" application note for details. 2.3 clock synthesizer the output of the core pll is connected to the clock synthesizer that generates twelve clocks and three frame pulses. 2.4 output clocks the zl30402 provides the following clocks (see figure 13 "st-bus and gci output timing", figure 14 "ds1, ds2 and c19o clock timing", figure 15 "c155o and c19o timing", and figure 18 "e3 and ds3 output timing" for details): - c1.5o : 1.544 mhz clock with nominal 50% duty cycle - c2o : 2.048 mhz clock with nominal 50% duty cycle - c4o : 4.096 mhz clock with nominal 50% duty cycle - c6o : 6.312 mhz clock with nominal 50% duty cycle - c8o : 8.192 mhz clock with nominal 50% duty cycle - c8.5o : 8.592 mhz clock with duty cycle from 30 to 70%. - c11o : 11.184 mhz clock with duty cycle from 30 to 70%. - c16o : 16.384 mhz clock with nominal 50% duty cycle - c19o : 19.44 mhz clock with nominal 50% duty cycle (with optional dejittering) - c34o : 34.368 mhz clock with nominal 50% duty cycle - c44o : 44.736 mhz clock with nominal 50% duty cycle - c155 : 155.52 mhz clock with nominal 50% duty cycle. the zl30402 provides the following fram e pulses (see figure 13 "st-bus and gci output timing" for details). all frame pulses have the same 125 s period (8khz frequency): - f0o : 244 ns wide, logic low frame pulse - f8o : 122 ns wide, logic high frame pulse - f16o : 61 ns wide, logic low frame pulse the clock synthesizer has an internal analog pll (apll) t hat can be placed in the path of the digitally generated clocks to multiply frequencies and reduce jitt er. the combination of two pins, e3ds3/oc3 and e3ds3, controls the placement of the apll and allows for selection of di fferent clock configurati ons e.g., if e3ds3/oc3 pin is low the 19.44 mhz clock is derived from 155.52 mhz clock with very low jitter. the same apll can be used to generate clocks with e3, ds3 or oc3 rates (see figure 4 "c1 9o, c155o, c34/c44 clock generation options" for details).
zl30402 data sheet 14 zarlink semiconductor inc. figure 4 - c19o, c155o, c34/c44 clock generation options all clocks and frame pulses except the c155 are out put with cmos logic levels. the c155 clock (155.52mhz) is output in a standard lvds format. 2.5 output clocks phase adjustment the zl30402 provides three control registers dedicated to programming the output clock phase offset. clocks c16o , c8o, c4o and c2o and frame pulses f16o , f8o, f0o are derived from 16.384 mhz and can be jointly shifted with respect to an active reference clock by up to 125 s with a step size of 61 ns. the required phase shift of clocks is programmable by writing to the phase offset register 2 ("table 8") and to the phase offset register 1 ("table 9"). the c1.5o clock can be shifted as well in step sizes of 81ns by programming c1.5poa bits in control register 3 ("table 11"). the coarse phase adjustment is augmented with a very fi ne phase offset control on the order of 477 ps per step. this fine adjustment is programmable by writing to the fine phase offset register (table 15 "fine phase offset register (r/w)"). the offset moves all clocks and frame pulses generated by zl30402 including c155 clock. 2.6 control state machine 2.6.1 clock modes any network element that operates in a synchronous netw ork must support three cl ock modes: free-run, normal (locked) and holdover. these clock modes determine behavior of a network element to the unforeseen changes in the network synchronization hierarchy. requirements for clock modes are defined in the international standards e.g.: g.813, gr-1244-core and gr-253- core and they are very strictly enforced by network operators. the zl30402 supports all clock modes and each of these mo des have a corresponding state in the control state machine. 2.6.2 zl30402 state machine the zl30402 control state machine is a complex combinat ion of many internal states supporting the three mandatory clock modes. the simplified version of this st ate machine is shown in figure 5 and it includes the mandatory states: free-run, normal and holdover. these three states are complemented by two additional states: reset and auto holdover, which are critical to the zl30402 operation under the changing external conditions. c155 output c19o output c34/44 output e3ds3/oc3 e3ds3/oc3 e3ds3/oc3 0 1 0 1 01 155.52 hiz 19.44 dejittered 19.44 11.184 44.736 8.592 34.368 e3/ds3 0 1 e3ds3/oc3 c155 output
zl30402 data sheet 15 zarlink semiconductor inc. figure 5 - zl30402 state machine 2.6.3 reset state the reset state must be entered when z l30402 is powered-up. in this state, a ll arithmetic calculations are halted, clocks are stopped, the microprocessor por t is disabled and all internal register s are reset to their default values. the reset state is entered by pulling the reset pin low for a minimum of 1 s. when the reset pin is pulled back high, internal logic starts a 500 s initialization process before switching into the free-run state (ms2, ms1 = 10). 2.6.4 free-run state (free-run mode) the free-run state is entered when synchr onization to the network is not requir ed or is not possible. typically this occurs during installation, repairs or when a network elem ent operates as a master node in an isolated network. in the free-run state, the accura cy of the generated clocks is determined by the accuracy and stability of the zl30402 master crystal oscillator. when equipment is installed for the first time (or periodically maintained) the accuracy of the free-run clocks can be adjusted to within 1x10 -12 by setting the offset frequency in the master clock frequency calibration register. 2.6.5 normal state (normal mode or locked mode) the normal state is entered when a good quality referenc e clock from the network is available for synchronization. the zl30402 automatically detects the frequency of the reference clock (8 khz, 1.544 mhz, 2.048 mhz or 19.44 mhz) and sets the lock status bit and pin high afte r acquiring synchronization. in the normal state all generated clocks (c1.5o, c2o, c4o , c6o, c8o, c16o , c19o, c34/c44 and c155) and frame pulses (f0o , f8o, f16o ) are derived from network timing. to guarantee uninterrupted synchronization, the zl30402 has two acquisition plls that continuously m onitor the quality of the incoming re ference clocks. this dual architecture enables quick replacement of a poor or failed refere nce and minimizes the time spent in other states. normal (locked) 00 auto hold- over hold- over 01 free- run 10 reset ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 == 01 or refsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr= 0-->1 then 1-->0 {manual} ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 & {auto} ms2, ms1 == 10 forces unconditional return from any state to free-run notes: ==: equal {auto}: automatic transition ! =: not equal auto holdover: automatic holdover & =: and operation 0 --> 1: transition from 0 to 1 state ms2, ms1 ms2, ms1! = 10 reset == 1 refsel change
zl30402 data sheet 16 zarlink semiconductor inc. 2.6.6 holdover state (holdover mode) the holdover state is typically entere d for short durations while network sync hronization is temporarily disrupted. in holdover mode, the zl30402 generates clocks, which are not locked to an external reference signal but their frequencies are based on stored coefficients in memory that were determined while the pll was in normal mode and locked to an external reference signal. the initial frequency offset of the zl30402 in holdover mode is 1x10 -12 . this is more accurate than telcordia?s gr- 1244-core stratum 3e requirement of + 1x10 -9 . once the zl30402 has transitioned into holdover mode, holdover stability is determined by the stability of the 20mhz master clock oscillator. selection of the oscillator requires close examination of the crysta l oscillator temperature sensitivity and frequency drift caused by aging. 2.6.7 auto holdover state the auto holdover state is a transiti onal state that the zl30402 enters automatically when the active reference fails unexpectedly. when the zl30402 detects loss of referenc e it sets the holdover status bit and waits in auto holdover state until the failed reference recovers. the holdover status may alert the control processor about the failure and in response the control processor may switch to the secondary reference clock. the auto holdover and holdover states are internally combined together and they are output as a holdover status on pin 55 and bit 4 in status register 1 (table 6 on page 22). 2.6.8 state transitions in a typical network element applic ation, the zl30402 will ty pically operate in norm al mode (ms2, ms1 == 00) generating synchronous clocks. its two acquisition plls wi ll continuously monitor the input references for signs of degraded quality and output status information for further processing. the status info rmation from the acquisition plls and the core pll combined with status information from line interfaces and framers (as listed below) forms the basis for creating reliable network synchronization. ? acquisition plls (pah, pafl, sah, safl) and ? core pll (lock, holdover, flim) ? line interfaces (e.g. los - loss of signal, ais - alarm indication signal) and ? framers (e.g. lof - loss of frame or synchronization status messages carried over sonet s1 byte or esf-ds1 facility data link). the zl30402 state machine is designed to perform some transitions automatically, leaving other less time dependent tasks to the control processor. the state mach ine includes two stimulus signals which are critical to automatic operation: ?ok --> fail? and ?fail --> ok? that re present loss (and recovery) of reference signal or its drift by more than 30000 ppm. both of them force the co re pll to transition into and out of the auto holdover state. the zl30402 state machine may also be driven by c ontrolling the mode select pins or bits ms2, ms1. in order to avoid network synchronization problems, the state machine has built-i n basic protection that does not allow switching the core pll into a state where it cannot operate correctly e.g. it is not possible to force the core pll into normal mode when all references are lost. 3.0 master clock fre quency calibration circuit in an ordinary timing generation mo dule, the free-run mode a ccuracy of generated clocks is determined by the accuracy of the master crystal oscillator. if the master crystal oscillator has a manufacturing tolerance of +/- 4.6 ppm, the generated clocks wi ll have no better accuracy. the zl30402 eliminates tolerance pr oblems by providing a programmable master clock frequency calibration circuit, which can reduce oscillator manufacturing tolerance to near zero. this feature eliminates the need for high precision 20 mhz crystal oscillators, which could be very expensive for equipment that has to maintain accuracy over a very long period of time (e .g., 20 years in some applications).
zl30402 data sheet 17 zarlink semiconductor inc. the compensation value for the master clock calibration register (mcfc3 to mcfc0) can be calculated from the following equation: mcfc = 45036 * ( - f offset ) where: f offset = f m - 20 000 000 hz the f m frequency should only be measured after the master crystal oscillator has been mounted inside a system and powered long enough for the master crystal oscillator to reach a steady operating te mperature. section 5.2 on page 31 provides two examples of how to calculate an of fset frequency and convert the decimal value to a binary format. the maximum frequency compensation range of the mcfc register is equal to 2384 ppm (47680 hz). 3.1 microprocessor interface the zl30402 can be controlled by a microprocessor or by an asic type of device that is connected directly to the hardware control pins. if the hw pin is tied low (see fi gure 6 "hardware and software control options"), an 8-bit motorola type microprocessor may be used to control pll operation and check its status. under software control, the control pins ms2, ms 1, fcs, refsel, refalign are disabled and they are replac ed by the equivalent control bits. the output pins lock and holdover are always active an d they provide current status information whether the device is in microprocessor or hardware control. software (microprocessor) control pr ovides additional functionality that is not available in har dware control such as output clock phase ad justment, master cloc k frequency calibration and extended access to status regist ers. these registers ar e also accessible when the zl30402 operates under hardware control. 3.2 jtag interface the zl30402 jtag (joint test action group) interfac e conforms to the boundary- scan standard ieee1149.1-1990, which specifies a design-for-testability tech nique called boundary-scan test (bst). the bst architecture is made up of four basic elements, test access port (tap), tap cont roller, instruction register (i r) and test data registers (tdr) and all these elements are implemented on the zl30402. zarlink semiconductor provides a boundary scan descri ption language (bsdl) file that contains all the information required for a jtag test system to access th e zl30402's boundary scan circuitry. the file is available for download from the zarlink semiconductor web site: www.zarlink.com. 4.0 hardware and software control the zl30402 offers hardware and software control options that simplify design of basic or complex clock synchronization modules. hardware control offers fewer fe atures but still allows for building of sophisticated timing cards without extensive programming. the complete set of control and status functions for each mode are shown in figure 6 "hardware and software control options".
zl30402 data sheet 18 zarlink semiconductor inc. figure 6 - hardware and software control options 4.1 hardware control the hardware control is a s ubset of software control and it will only be briefly described with cross-referencing to software control programmable registers. 4.1.1 control pins the zl30402 has six dedicated control pins for selecting modes of operation and acti vating different functions. these pins are listed below: ms2 and ms1 pins : mode select : the ms2 (pin 19) and ms1 (pin 18) inputs select the pll mode of operation. see table 1 for details. the logic level at these inputs is sampled by the rising edge of the f8o frame pulse. fcs pin : filter charact eristic select . the fcs (pin 9) input is used to sele ct the filtering char acteristics of the core pll. see table 2 on page 19 for details. ms2 ms1 mode of operation 0 0 normal mode 0 1 holdover mode 10free-run 11reserved table 1 - operating modes and states hardware control software control hw = 1 c o n t r o l s t a t u s c o n t r o l s t a t u s ms2 ms1 fcs refsel refalign ahrd mhr hw = 0 lock holdover flim pah pafl sah safl p pins lock holdover ms2 ms1 fcs refsel refalign
zl30402 data sheet 19 zarlink semiconductor inc. refsel : reference source select . the refsel (pin 47) input selects t he pri (primary) or sec (secondary) input as the reference clock for the core pll. the logic level at this input is sampled by the rising edge of f8o. refalign : reference align . the refalign (pin 48) input controls phase rea lignment between the input reference and the generated output clocks. 4.1.2 status pins the zl30402 has two dedicated status pins for indicating modes of operation. these pins are listed below: lock . this output goes high when the core pll is locked to the selected acquisition pll. holdover - this output goes high when the core pll ente rs holdover mode. the core pll will switch to holdover mode if the respective acquisition pll enters hol dover mode or if the mode select pins or bits are set to holdover (ms2, ms1 = 01). 4.2 software control software control is enabled by setting the hw pin to logi c zero (hw = 0). in this mode all hardware control pins (inputs) are disabled and status bits (outputs) are enabled. the zl30402 has seventeen registers that provide all the functionality available in hardware control and in add ition they offer advanced control and monitoring that is only available in software control (see figur e 6 "hardware and software control options"). 4.2.1 control bits the zl30402 has seven control bits as is shown in figure 6 "hardware and software control options". the first five bits replace the five hardware control pi ns: ms2, ms1, fcs, refsel and refalign and the last two bits support recovery from auto holdover mode: ahrd and mh r. these bits are described in section 3.2.4. in addition to the control bits shown in figure 6 "h ardware and software control options", the zl30402 has a number of bits and registers that are accessed infrequently or during co nfiguration only e. g., phase offset adjustment or master cl ock frequency calibration. fcs filtering characteristic phase slope 0 filter corner frequency set to 1.1 hz. this selection meets requirements of g.813 option 1 and gr-1244 stratum 3 clocks. 41ns in 1.326ms 1 filter corner frequency set to 0.1 hz. this selection meets requirements of g.813 option 2, gr-253 for sonet stratum 3 and gr-253 for sonet minimum clocks (smc). 885ns/s table 2 - filter characteristic selection refsel input reference 0 core pll connected to the primary acquisition pll 1 core pll connected to the secondary acquisition pll table 3 - reference source select
zl30402 data sheet 20 zarlink semiconductor inc. 4.2.2 status bits the zl30402 has seven status bits (see figure 6 "hardwar e and software control options"). the first two bits perform the same function as their equiva lent status pins. the last five bits perform two functions. bits flim, pafl, safl indicate drift of the reference clock frequencies beyo nd the capture range of acquisition and core plls and bits pah and sah show entry of primary and secondary ac quisition plls into holdover mode. these bits are described in detail in section 3.2.4. th e status pins are enabled when the zl30402 operates in software control and they can be used to trigger interrupts. 4.2.3 zl30402 register map addresses: 00h to 6fh note: the zl30402 uses address space from 00h to 6fh. registers at address locations not listed above must not be written or rea d. address hex register read write function 00 control register 1 r/w refsel, 0, 0, ms2, ms1, fcs, 0, refalign 01 status register 1 r rsv, rsv, lock, holdover , rsv, flim, rsv, rsv 04 control register 2 r/w e3ds3/oc3 , e3/ds3 , 0, 0, 0, 0, 0, 0, 06 phase offset register 2 r/w 0, 0, 0, 0, offen, c16poa10, c16poa9, c16poa8 07 phase offset register 1 r/w c16poa7, c16poa6, c16poa5, c16poa4, c16poa3, c16poa2, c16poa1, c16poa0 0f device id register r 0010 0001 11 control register 3 r/w rsv, rsv, c1.5poa2, c1.5poa1, c1.5poa0, 0, 0, 0 13 clock disable register 1 r/w 0, 0, c16dis, c8dis, c4dis, c2dis, c1.5dis,0 14 clock disable register 2 r/w 0, 0, 0, f8odis, f0odis, f16odis, c6dis, c19dis 19 core pll control register r/w 0, 0, 0, 0, 0, 0, mhr, ahrd, 0 1a fine phase offset register r/w fpoa7, fpoa6, fpoa5, fpoa4, fpoa3, fpoa2, fpoa1, fpoa0 20 primary acquisition pll status register r rsv, rsv, rsv, rsv, inpfreq1, inpfreq0, rsv, pah,pafl 28 secondary acquisition pll status register r rsv, rsv, rsv, rsv, inpfreq1, inpfreq0, rsv, sah, safl 40 master clock frequency calibration register - byte 4 r/w mcfc31, mcfc30, mcfc29, mcfc28, mcfc27, mcfc26, mcfc25, mcfc24, 41 master clock frequency calibration register - byte 3 r/w mcfc23, mcfc22, mcfc21, mcfc20, mcfc19, mcfc18, mcfc17, mcfc16 42 master clock frequency calibration register - byte 2 r/w mcfc15, mcfc14, mcfc13, mcfc12, mcfc11, mcfc10, mcfc9, mcfc8 43 master clock frequency calibration register - byte 1 r/w mcfc7, mcfc6, mcfc5, mcfc4, mcfc3, mcfc2, mcfc1, mcfc0 table 4 - zl30402 register map
zl30402 data sheet 21 zarlink semiconductor inc. 4.2.4 register description address: 00 h bit name functional description default 7refsel reference select . a zero selects the pri (primary) reference source as the input reference signal a nd a one selects the sec (secondary) reference. 0 6-5 rsv reserved . 00 4-3 ms2, ms1 mode select - ms2 = 0 ms1 = 0 normal mode (locked mode) - ms2 = 0 ms1 = 1 holdover mode - ms2 = 1 ms1 = 0 free-run mode - ms2 = 1 ms1 = 1 reserved 10 2fcs filter characte ristic select fcs = 0 filter corner frequency set to 1.1 hz. this selection meets requirements of g.813 option 1 and gr-1244 stratum 3 clocks. fcs = 1 filter corner frequency set to 0.1 hz. this selection meets requirements of g.813 option 2, gr-253 for sonet stratum 3 and gr-253 for sonet minimum clocks (smc). 0 1rsv reserved . 0 0 refalign reference align . a high-to-low transition aligns the generated output clocks to the input reference signal. the maximum phase slope depends on the filter characteri stic selected and is limited to: - 41ns in 1.326ms for fcs = 0 - 885 ns in 1s for fcs = 1 1 table 5 - control register 1 (r/w)
zl30402 data sheet 22 zarlink semiconductor inc. address: 01 h address: 04 h bit name functional description 7rsv reserved. 6rsv reserved. 5lock lock . this bit goes high when the core pll is locked to the selected acquisition pll. 4 holdover holdover . this bit goes high when the core pll enters holdover mode. detection of reference failure and subsequent transiti on from normal to holdover state takes approximately: 0.750 s for 19.44 mhz reference, 0.850 s for 2.048 mhz reference, 1.1 s for 1.544 mhz reference and 130 s for 8 khz reference. 3rsv reserved . 2flim frequency limit . this bit goes high when the core pll is pulled by the input reference signal to the edge of its fr equency tracking range set at 104 ppm. this bit may change state momentarily in the event of large jitter or wander excursions occurring when the input reference is close to the frequency limit range. 1rsv reserved . 0rsv reserved . table 6 - status register 1 (r) bit name functional description default 7 e3ds3/oc3 e3, ds3 or oc-3 clock select . setting this bit to zero enables the c155p/n outputs (pin 30 and pin 31) and enables the c34/c44 output (pin 53) to provide c8 or c11 clocks. logic high sets the c155 clock outputs into high impedance and enables the c34/c44 output to provide a c34 or c44 clock. 0 6e3/ds3 e3 or ds3 clock select . when e3ds3/oc3 bit is set high, a logic low on the e3/ds3 bit selects a 44.736 mhz clock on the c34/c44 output and logic high selects a 34.368 mhz clock. when the e3ds3/oc3 bit is set low, a logic low on the e3/ds3 bit selects an 11.184 mhz clock on the c34/c44 output and a logic high selects an 8.592 mhz clock. 0 5-0 rsv reserved. 000000 table 7 - control register 2 (r/w)
zl30402 data sheet 23 zarlink semiconductor inc. address: 06 h address: 07 h address: 0f h bit name functional description default 7-4 rsv reserved . 0000 3offen offset enable . set high to enable programmable phase offset adjustments (c16 phase offset adjustment and c1.5 phase offset adjustment) between the input reference and the generated clocks. 0 2 - 0 c16poa10 to c16poa8 c16 phase offset adjustment . these three bits (most significant) in conjunction with the eight bits of phase offset register 1 allow for phase shifting of all clocks and frame pulses that are derived from the c16 clock (c8o, c4o , c2o, f16o , f8o, f0o). the phase offset is an unsigned number in a range from 0 to 2047. each increment by one represents phase-offset advancement by 61.035 ns with respect to the input reference signal. the phase offset is a two-byte value and it must be written in one step increment s. for example: four writes are required to advance clocks by 244 ns fr om its current position of 22h: write 23h, 24h, 25h, 26h. writing num bers in reverse order will delay clocks from their present position. 000 table 8 - phase offset register 2 (r/w) bit name functional description default 7-0 c16poa7 to c16poa0 c16 phase offset adjustment . the eight least significant bits of the phase offset adjustment word. see the phase offset register 2 for details. 0000 0000 table 9 - phase offset register 1 (r/w) bit name functional description 7-4 id7 - 4 device identification number . these four bits represent the device part number. the id number for zl30402 is 0010. 3-0 id3 - 0 device revision number . these bits represent the revision number. number starts from 0001. table 10 - device id register (r)
zl30402 data sheet 24 zarlink semiconductor inc. address: 11 h address: 13 h bit name functional description default 7rsv reserved . 0 6rsv reserved. 0 5-3 c1.5poa2 to c1.5poa0 c1.5 phase offset adjustment . these three bits allow for changing of the phase offset of the c1.5o clock rela tive to the active input reference. the phase offset is an unsigned number in a range from 0 to 7. each increment by one represents phas e-offset advancement by 80.96 ns. example: writing 010 advances c1.5 clock by 162 ns. successive writing of 001 delays this clock by 80.96 ns from its present position 000 2-0 rsv reserved . 000 table 11 - control register 3 (r/w) bit name functional description default 7rsv reserved . 0 6rsv reserved . 0 5 c16dis 16.384 mhz clock disable . when set high, this bit tristates the 16.384 mhz clock output. 0 4c8dis 8.192 mhz clock disable. when set high, this bit tristates the 8.192 mhz clock output. 0 3c4dis 4.096 mhz clock disable . when set high, this bit tristates the 4.096 mhz clock output. 0 2c2dis 2.048 mhz clock disable . when set high, this bit tristates the 2.048 mhz clock output. 0 1 c1.5dis 1.544 mhz clock disable . when set high, this bit tristates the 1.544 mhz clock output. 0 0rsv reserved . 0 table 12 - clock disable register 1 (r/w)
zl30402 data sheet 25 zarlink semiconductor inc. address: 14 h address: 19 h bit name functional description default 7-5 rsv reserved . 000 4 f8odis f8o frame pulse disable . when set high, this bit tristates the 8 khz 122 ns active high framing pulse output. 0 3 f0odis f0o frame pulse disable . when set high, this bit tristates the 8 khz 244 ns active low framing pulse output. 0 2 f16odis f16o frame pulse disable . when set high, this bit tristates the 8 khz 61 ns active low framing pulse output. 0 1c6dis 6.312 mhz clock disable . when set high, this bit tristates the 6.312 mhz clock output. 0 0 c19dis 19.44 mhz clock disable . when set high, this bit tristates the 19.44 mhz clock output. 0 table 13 - clock disable register 2 (r/w) bit name functional description default 7-3 rsv reserved . 00000 2mhr manual holdover release . a change form 0 to 1 on the mhr bit will release the core pll from auto holdover to normal when aut omatic return from holdover is disabled (ahrd is set to 1). this bit is level sensitiv e and it must be cleared immediately after it is set to 1 (next write operation). this bit has no effect if ahrd is set to 0. 0 1 ahrd automatic holdover return disable . when set high, this bit inhibits the core pll from automatically switching back to normal mode from auto holdover state when the active acquisition pll regains lock to input reference. the active acquisition pll is the acquisition pll to which the core pll is currently connected. 0 0rsv reserved . 0 table 14 - core pll control register (r/w)
zl30402 data sheet 26 zarlink semiconductor inc. address: 1a h address: 20 h bit name functional description default 7-0 fpoa7 - 0 fine phase offset adjustment . this register allows p hase offset adjustment of all output clocks and frame pulses (c 16o , c8o, c4o , c2o, f16o , f8o, f0o , c155, c19o, c34/44, c1.5o, c6o) relative to t he active input refer ence. the adjustment can be positive (advance) or negative (delay) with a nominal step size of 477 ps (61.035 ns / 128). the rate of phase change is limited to 885 ns/s for fcs = 1 and 41 ns in 1.326 ms for fcs = 0 selections. the phase offset value is a signed 2?s complement number e.g.: advance: +1 step = 01h, +2 steps = 02h, +127 steps = efh delay: -1 step = ffh, -2 steps = feh, -128 steps = 80h example: writing 08h advances all clocks by 3.8 ns and writing f3h delays all clocks 00000 000 table 15 - fine phase offset register (r/w) bit name functional description 7-5 rsv reserved . 4-3 inpfreq1- 0 input frequency . these two bits identify the pr imary reference clock frequency. - 00 = 19.44 mhz - 01 = 8 khz - 10 = 1.544 mhz - 11 = 2.048 mhz 2rsv reserved . 1pah primary acquisition pll holdover . this bit goes high whenever the acquisition pll enters holdover mode. holdover mode is entered when the reference frequency is - lost completely - drifts more than 30 000 ppm off from the nominal frequency - a large phase hit occurs on the reference clock. 0pafl primary acquisition pll frequency limit . this bit goes high whenever the acquisition pll exceeds its capture range of 104 ppm. this bit can flicker high in the event of a large excursion of still tolerable input jitter. table 16 - primary acquisition pll status register (r)
zl30402 data sheet 27 zarlink semiconductor inc. address: 28 h address: 40 h address: 41 h address: 42 h bit name functional description 7-5 rsv reserved . 4-3 inpfreq1-0 input frequency . these two bits identify the secondary reference clock frequency. - 00 = 19.44 mhz - 01 = 8 khz - 10 = 1.544 mhz - 11 = 2.048 mhz 2rsv reserved . 1 sah secondary acquisition pll holdover . this bit goes high whenever the acquisition pll enters holdover mode. holdover mode is entered when reference frequency is: - lost completely - drifts more than 30 000 ppm off the nominal frequency - a large phase hit occurs on the reference clock. 0 safl secondary acquisition pll frequency limit . this bit goes high whenever the acquisition pll exceeds its capture range of 104 ppm. this bit can flicker high in the event of a large excursion of still tolerable input jitter. table 17 - secondary acquisition pll status register (r) bit name functional description default 7-0 mcfc31 - 24 master clock freq uency calibration . this most significant byte contains the 31st to 24th bit of the master cl ock frequency calibration register. see applications section 4.2 for a detailed de scription of how to calculate the mcfc value. 00000 000 table 18 - master clock frequency calibration register 4 (r/w) bit name functional description default 7-0 mcfc23 - 16 master clock frequency calibration . this byte contains the 23rd to 16th bit of the master clo ck frequency calibr ation register. 00000 000 table 19 - master clock frequency calibration register 3 (r/w) bit name functional description default 7-0 mcfc15 - 8 master clock frequency calibration . this byte contains the 15th to 8th bit of the master cloc k frequency calibration register. 00000 000 table 20 - master clock frequency calibration register 2 (r/w)
zl30402 data sheet 28 zarlink semiconductor inc. address: 43 h 5.0 applications this section contains application specific details for mode switching and master cloc k oscillator calibration. 5.1 zl30402 mode switching - examples the zl30402 is designed to transition from one mode to the other driven by the internal state machine or by manual control. the following exampl es present a couple of typical scenari os of how the zl30402 can be employed in network synchronization equipment (e.g., timing modules, line cards or stand alone synchronizers). 5.1.1 system start-up sequence: free-run --> holdover --> normal the free-run to holdover to normal transition represen ts a sequence of steps that will most likely occur during a new system installation or scheduled maintenance of timing cards. the process starts from the reset state and then transitions to free-run m ode where the system (card) is being initialized. at the end of this process the zl30402 should be switched into normal mode (with ms 2, ms1 set to 00) instead of holdover mode. if the reference clock is available, the zl304 02 will transition briefly in to holdover to acquire synchronization and switch automatically to normal mode. if the reference clock is not available at this time, as it may happen during new system installation, then the zl30402 will stay in holdover indefinitely. while in holdover mode, the core pll will continue generating clocks with the same accuracy as in the free-run mode, waiting for a good reference clock. when the system is connected to the network (or timing ca rd switched to a valid reference) the acquisition pll will quickly synchronize and clear its own holdover status (p ah bit). this will enable the core pll to start the synchronization process. after acquiring lock, the zl30402 will automatically switch from holdover into normal mode without system interven tion. this transition to the normal mode will be flagged by the lock status bit and pin. figure 7 - transition from free-run to normal mode bit name functional description default 7-0 mcfc7 - 0 master clock frequency calibration . this byte contains bit 7 to bit 0 of the master clock frequency calibration register. 00000 000 table 21 - master clock frequency calibration register 1 (r/w) normal (locked) 00 auto hold- over hold- over 01 free- run 10 reset ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 == 01 or refsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr= 0 -->1 then 1-->0 {manual} ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 {auto} ms2, ms1 == 10 forces unconditional return from any state to free-run ms2, ms1! = 10 reset == 1 refsel change
zl30402 data sheet 29 zarlink semiconductor inc. 5.1.2 single reference operation: normal --> auto holdover --> normal the normal to auto-holdover to normal transition will usually happen when the network element loses its single reference clock unexpectedly or when it has tw o references but switching to the secondary reference is not a desirable option (unless prim ary reference is lost without chance of quick recovery). the sequence starts with the unexpected failure of a refere nce signal shown as transition ok --> fail in figure 7 "transition from free-run to normal mode" at a time when zl30402 operates in normal mode. this failure is detected by the active acquisition pll based on the following fail criteria: ? frequency offset on 8 khz, 1.544 mhz, 2.048 mhz and 19.44 mhz reference clocks exceeds 30000 ppm (3%). ? single phase hit on 1.544 mhz, 2.048 mhz and 19.44 mhz exceeds half of the cycle of the reference clock. after detecting any of these anomalies on a reference clock the acquisition pll will switch itself into holdover mode forcing the core pll to automatically switch into the auto holdover state. this condition is flagged by lock = 0 and holdover = 1. figure 8 - automatic entry in to auto holdover state and eecovery into normal mode there are two possible returns to normal mode after the reference signal is restored: ? with the ahrd (automatic holdover return disable) bit se t to 0. in this case the core pll will automatically return to the normal state after the reference signal recovers from failure. this transition is shown on the state diagram as a fail --> ok change. this change becomes effective when the reference is restored and there have been no phase hits detected for at least 64 clock cycles for 1.544/2.048 mhz reference, 512 clock cycles for 19.44 mhz reference and 1 clock cycle for 8 khz reference. ? with the ahrd bit set to high to disable automatic return to normal and the change of mhr (manual holdover release) bit from 0 to 1 to trigger the tran sition from auto holdover to normal. this option is provided to protect the core pll against toggling between normal and auto holdover states in case of an intermittent quality reference clock. in the case when mhr has been changed when the reference is still not available (acquisition pll in holdover mode) the trans ition to normal state will not occur and mhr 0 to 1 transition must be repeated. this transition from auto holdover to normal m ode is performed as ?hitless? reference switching. normal (locked) 00 auto hold- over hold- over 01 free- run 10 reset ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 == 01 or refsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr=0 -->1 then 1-->0 {manual} ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 {auto} ms2, ms1 == 10 forces unconditional return from any state to free-run ms2, ms1! = 10 reset == 1 refsel change automatic return to normal: ahrd=0 or manual return to normal: ahrd=1 & mhr= 0-->1 then 1-->0
zl30402 data sheet 30 zarlink semiconductor inc. 5.1.3 dual reference operation: normal --> auto holdover--> holdover --> normal the normal to auto-holdover to holdover to norm al sequence represents the most likely operation of zl30402 in network equipment. the sequence starts from the normal state and transitions to auto holdover state due to an unforeseen loss of reference. the failure conditions trig gering this transition were described in section 4.1.2. when in the auto holdover state, the zl30402 can return to normal mode automatically if the lost reference is restored and the adhr bit is set to 0. if the reference clock failure persist s for a period of time that exceeds the system design limit, the system control processor may initiate a reference sw itch. if the secondary reference is available the zl30402 will briefly switch into holdover mode and then tr ansition to normal mode. figure 9 - entry into auto holdover state a nd recovery into normal mode by switching references the new reference clock will most like ly have a different phase but it may al so have a different fractional frequency offset. in order to lock to a new reference with a different frequency, the core pll may be stepped gradually towards the new frequency. the frequency slope will be limited to less than 2.0 ppm/sec. normal (locked) 00 auto hold- over hold- over 01 free- run 10 reset ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 == 01 or refsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr= 0-->1 then 1-->0 {manual} ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 {auto} ms2, ms1 == 10 forces unconditional return from any state to free-run ms2, ms1! = 10 reset == 1 refsel change ahrd=0 (automatic return enabled)
zl30402 data sheet 31 zarlink semiconductor inc. 5.1.4 reference switching (refsel): normal --> holdover --> normal the normal to holdover to normal mode switching is usually performed when: ? a reference clock is available but its frequency drifts be yond some specified limit. in a network element with stratum 3 internal clocks, the reference failure is declared when its frequency drifts more than 12 ppm beyond its nominal frequency. ? during routine maintenance of equipment when orderly sw itching of reference clocks is possible. this may happen when synchronization references must be rearrang ed or when a faulty line card must be replaced. figure 10 - manual reference switching two types of transitions are possible: ? semi-automatic transition, which involves changing re fsel input to select a secondary reference clock without changing the mode select inputs ms2, ms 1 = 00 (normal mode). this forces zl30402 to momentarily transition through the holdover state and automatically return to normal mode after synchronizing to a secondary reference clock. ? manual transition, which involves switching into hol dover mode (ms2, ms1 = 01), changing references with refsel, and manual return to the normal mode (ms2, ms1 = 00). in both cases, the change of refer ences provides ?hitless? switching. 5.2 programming master clock os cillator frequency calibration register the master crystal oscillator and its programmable mast er clock frequency calibrati on register (see table 18, table 19, table 20, and table 21) have been described in section 3.0 "master clock frequency calibration circuit", on page 16. programming of this re gister should be done after system has been powered long enough for the master crystal oscillator to reach a steady operating temperature. when t he temperature stabilizes the crystal oscillator frequency should be measured with an accurate frequency meter. the frequency measurement should be substituted for the f offset variable in the following equation. mcfc = 45036 * ( - f offset ) where f offset is the crystal oscillat or frequency offset from the nominal 20 000 000 hz frequency expressed in hz. normal (locked) 00 auto hold- over hold- over 01 free- run 10 reset ref: ok & ms2, ms1 == 00 {auto} ref: ok --> fail & ms2, ms1 == 00 {auto} ms2, ms1 == 01 or refsel change ref: fail --> ok & ms2, ms1 == 00 & ahrd=1 & mhr= 0-->1 then 1-->0 {manual} ref: fail --> ok & ms2, ms1 == 00 & ahrd=0 {auto} ms2, ms1 == 10 forces unconditional return from any state to free-run ms2, ms1! = 10 reset == 1 refsel change
zl30402 data sheet 32 zarlink semiconductor inc. example 1 : calculate the binary value that must be written to the mcfc register to correct a -1ppm offset of the master crystal oscillator. the -1ppm offset for a 20 mhz frequency is equivalent to -20 hz: mcfc = 45036 * 20 = 900720 = 00 0d be 70 h note: correcting the -1ppm crystal offset requires +1ppm mcfc offset. example 2 : calculate the binary value that must be written to the mcfc register to correct a +2 ppm offset of the master crystal oscillator. the +2 ppm offset for 20 mhz frequency is equivalent to 40 hz: mcfc = 45036 * (-40) = -1801440 = ff e4 83 20 h 6.0 characteristics 6.1 ac and dc electr ical characteristics * voltages are with respect to ground (gnd) unless otherwise stated * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. * voltages are with respect to ground (gnd) unless otherwise stated absolute maximum ratings* parameter symbol min. max. units 1 supply voltage v ddr -0.3 7.0 v 2 voltage on any pin v pin -0.3 vdd+0.3 v 3 current on any pin i pin 30 ma 4 storage temperature t st -55 125 c 5 package power dissipation (80 pin lqfp) p pd 1000 mw 6 esd rating v esd 1500 v recommended operating conditions * characteristics symbol min. typ. max. units 1 supply voltage v dd 3.0 3.3 3.6 v 2 operating temperature t a -40 25 +85 c
zl30402 data sheet 33 zarlink semiconductor inc. * voltages are with respect to ground (gnd) unless otherwise stated note 1: v os is defined as (v oh + v ol ) / 2 note 2: rise and fall times are measured at 20% and 80% levels. * voltages are with respect to ground (gnd) unless otherwise stated * supply voltage and operating temperature are as per recommended operating conditions * timing for input and output signals is based on the worst case conditions (over t a and v dd ) figure 11 - timing parameters measurement voltage levels dc electrical characteristics* characteristics symbol min. max. units notes 1 supply current with c20i = 20 mhz i dd 135 ma outputs unloaded 2 supply current with c20i = 0v i dds 2.2 ma outputs unloaded 3 cmos high-level input voltage v cih 0.7v dd v 4 cmos low-level input voltage v cil 0.3v dd v 5 input leakage current i il 15 av i =v dd or gnd 6 high-level output voltage v oh 2.4 v i oh =10 ma 7 low-level output voltage v ol 0.4 v i ol =10 ma 8 lvds: differential output voltage v od 250 450 mv z t =100 ? 9 lvds: change in vod between complementary output states dv od 50 mv z t =100 ? 10 lvds: offset voltage v os 1.125 1.375 v note 1 11 lvds: change in vos between complementary output states dv os 50 mv 12 lvds: output short circuit current i os 24 ma pin short to gnd 13 lvds: output rise and fall times t rf 260 900 ps note 2 ac electrical character istics - timing parameter measurement - cmos voltage levels * characteristics symbol level units 1 threshold voltage v t 0.5v dd v 2 rise and fall threshold voltage high v hm 0.7v dd v 3 rise and fall threshold voltage low v lm 0.3v dd v all signals timing reference points v hm v t v lm t if, t of t ir, t or
zl30402 data sheet 34 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions figure 12 - microport timing ac electrical characteristi cs - microprocessor timing* characteristics symbol min. max. units notes 1 ds low t dsl 65 ns 2 ds high t dsh 100 ns 3 cs setup t css 0ns 4 cs -hold t csh 0ns 5 r/w setup t rws 20 ns 6 r/w hold t rwh 5ns 7 address setup t ads 10 ns 8 address hold t adh 10 ns 9 data read delay t drd 60 ns c l =90 pf 10 data read hold t drh 10 ns 11 data write setup t dws 10 ns 12 data write hold t dwh 5ns ds cs r/w a0-a6 d0-d7 read d0-d7 write t css t rws t ads t csh t rwh t adh t dws t drd t dwh valid data t dsl v t v t v t v t v t t dsh t drh v t valid data
zl30402 data sheet 35 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions figure 13 - st-bus and gci output timing ac electrical charact eristics - st-bus and gci output timing* characteristics symbol min. max. units notes 1 f16o pulse width low (nom 61ns) t f16l 52 61 ns 2 f8o to f16o delay t f16d 19 27 ns 3 c16o pulse width low t c16l 19 35 ns 4 c16o to f8o delay t c16d -2 6 ns 5 f8o pulse width high (nom 122 ns) t f8h 118 128 ns 6 c8o pulse width low t c8l 54 65 ns 7 c8o to f8o delay t c8d -2 6 ns 8 f0o pulse width low (nom 244) t f0l 236 248 ns 9 f8o to f0o delay t f0d 115 123 ns 10 c4o pulse width low t c4l 114 126 ns 11 c4o to f8o delay t c4d 28ns 12 c2o pulse width low t c2l 235 250 ns 13 c2o to f8o delay t c2d -2 6 ns t f16l t f16d t c16d v t tc =125 s tc = 61.04 ns t f8h t c8l t c8d t f0l t f0d tc =125 s tc = 122.07 ns tc =125 s tc = 244.14 ns tc = 488.28 ns t c4l t c4d t c2d t c2l f16o f8o c16o c8o f0o c4o c2o t c16l v t v t v t v t v t v t
zl30402 data sheet 36 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions figure 14 - ds1, ds2 and c19o clock timing ac electrical character istics - ds1, ds2 and c19o clock timing* characteristics symbol min. max. units notes 1 c6o pulse width low t c6l 70 83 ns 2 f8o to c6o delay t c6d 80 95 ns 3 c1.5o pulse width low t c1.5l 315 330 ns 4 c1.5o to f8o delay t c1.5d 55 75 ns 5 c19o pulse width high t c19h 19 35 ns 6 c19o to f8o delay t c19d 814ns f8o c6o c1 . 5o c19o tc =125 s tc = 158.43 ns t c6d t c1.5d t c19d t c19h v t v t v t v t t c1.5l tc = 51.44 ns t c6l tc = 647.67 ns
zl30402 data sheet 37 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions figure 15 - c155o and c19o timing ac electrical character istics - c155o and c19o clock timing characteristics symbol min. max. units notes 1 c155o pulse width low t c155l 2.7 3.7 ns 2 c155o to c19o rising edge delay t cf19dlh -10 5 ns 3 c155o to c19o falling edge delay t cf19dhl -7 7 ns 4 c19 pulse width high t cf19h 22 33 t c155l t cf19dlh t cf19dhl 1.25v v t tc = 6.43 ns tc = 51.44 ns note: delay is measured from the rising edge of c155p clock (single ended) at 1.25v threshold to the rising and falling edges of c19o clock at v t threshold c155p c19o dejittered 123456 781 t cf19h
zl30402 data sheet 38 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions note 1: for 8 khz reference alignment refer to application note zl-27 "phase alignment between 8 khz output and 8 khz input ref erence on zl30402" figure 16 - input reference to output clock phase alignment ac electrical characteristics - input to output phase alignment (after refalign change from 1 to 0) * characteristics symbol min. max. units notes 1 8 khz ref pulse width high t r8h 100 ns 2 f8o to 8 khz ref input delay t r8d -15 115 ns note 1 3 1.544 mhz ref pulse width high t r1.5h 100 ns 4 1.544 mhz ref input to f8o delay t r1.5d 210 220 ns 5 2.048 mhz ref pulse width high t r2h 100 ns 6 2.048 mhz ref input to f8o delay t r2d 192 202 ns 7 19.44 mhz ref pulse width high t r19h 20 ns 8 f8o to 19.44 mhz ref input delay t r19d 514ns 9 19.44 mhz ref input to c19o delay t r19c19d -4 4 ns 10 reference input rise and fall time t ir , t if 10 ns t r8d t r1.5d t r2d t r19d t r8h t r1.5h t r2h t r19h t r19c19d tc = 125 s tc = 647.67 ns tc = 488.28 ns tc = 51.44 ns tc = 51.44 ns tc = 125 s pri/sec 8 khz pri/sec 1.544 mhz pri/sec 2.048 mhz pri/sec 19.44 mhz c19o f8o v t v t v t v t v t v t note: delay time measurements are done with jitter free input reference signals
zl30402 data sheet 39 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. figure 17 - input control si gnal setup and hold time * supply voltage and operating temperature are as per recommended operating conditions figure 18 - e3 and ds3 output timing ac electrical characteristi cs - input control signals * characteristics symbol min. max. units notes 1 input controls setup time t s 100 ns 2 input controls hold time t h 100 ns ac electrical characteristics - e3 and ds3 output timing* characteristics symbol min. max. units notes 1 c44o clock pulse width high t c44h 812ns 2 c11o clock pulse width high t c11h 840ns 3 c34o clock pulse width high t c34h 12 15 ns 4 c8.5o clock pulse width high t c8.5l 740ns t s v t v t t h f8o ms1, ms2 refsel, fcs, refalign e3/ds3 , e3ds3/oc3 t c44h v t t c34h t c8.5h c44o tc = 22.35 ns tc = 89.41 ns tc = 29.10 ns tc = 116.39 ns c11o c34o c8.5o v t v t v t t c11h
zl30402 data sheet 40 zarlink semiconductor inc. 6.2 performance characteristics * supply voltage and operating temperature are as per recommended operating conditions. performance characteristics* characteristics typical units notes 1 holdover accuracy 0.000001 ppm 2 holdover stability na ppm determined by stability of 20mhz frequency source 3 capture range 104 ppm lock time 4 1.1hz filter 70 s 4.6ppm frequency offset 5 0.1hz filter 70 s 4.6ppm frequency offset output phase variation 6 reference switching: pri ? sec, sec ? pri 50 ns 7 switching from normal mode to holdover mode 0ns 8 switching from holdover mode to normal mode 50 ns output phase slope 9 g.813 option 1, gr-1244 stratum 3 41 1.326ms 10 g.813 option 2 gr-253 sonet stratum 3 gr-253 sonet smc 885 ns/s
zl30402 data sheet 41 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. performance characteristics - jitter ge neration (intrinsic jitter) - filtered * characteristics max ulpp max ns-pp notes 1 c1.5o (1.544 mhz) 0.004 2.75 filter: 10 hz - 40 khz 2 c2o (2.048 mhz) 0.004 1.80 filter: 20 hz - 100 khz 3 c19o (19.44 mhz) dejittered 0.017 0.86 filter: 100 hz - 400 khz oc-1 4 c19o (19.44 mhz) dejittered 0.014 0.73 filter: 20 khz - 400 khz oc-1 5 c19o (19.44 mhz) dejittered 0.024 1.24 filter: 500 hz - 1.3 mhz oc-3 6 c19o (19.44 mhz) dejittered 0.021 1.08 filter: 65 khz - 1.3 mhz oc-3 7 c19o (19.44 mhz) 0.026 1.34 filter: 100 hz - 400 khz oc-1 8 c19o (19.44 mhz) 0.018 0.94 filter: 20 khz - 400 khz oc-1 9 c19o (19.44 mhz) 0.035 1.78 filter: 500 hz - 1.3 mhz oc-3 10 c19o (19.44 mhz) 0.025 1.30 filter: 65 khz - 1.3 mhz oc-3 11 c34o (34.368 mhz) 0.038 1.11 filter: 100 hz - 800 khz 12 c34o (34.368 mhz) 0.037 1.06 filter: 10 khz - 800 khz 13 c44o (44.736 mhz) 0.032 0.72 filter: 10 hz - 400 khz 14 c44o (44.736 mhz) 0.023 0.51 filter: 30 khz - 400 khz 15 c155o (155.52 mhz) 0.106 0.68 filter: 100 hz - 400 khz oc-1 16 c155o (155.52 mhz) 0.091 0.58 filter: 20 khz - 400 khz oc-1 17 c155o (155.52 mhz) 0.145 0.93 filter: 500 hz - 1.3 mhz oc-3 18 c155o (155.52 mhz) 0.127 0.82 filter: 65 khz - 1.3 mhz oc-3
zl30402 data sheet 42 zarlink semiconductor inc. * supply voltage and operating temperature are as per recommended operating conditions. performance characteristics - jitter gene ration (intrinsic jitter) - unfiltered * characteristics max ulpp max ns-pp notes 1 c1.5o (1.544 mhz) 0.010 6.5 2 c2o (2.048 mhz) 0.010 5.8 3 c4o- (4.096 mhz) 0.020 4.8 4 c6o (6.312 mhz) 0.033 5.2 5 c8o (8.192 mhz) 0.042 5.2 6 c8.5o (8.592 mhz) 0.028 3.3 7 c11o (11.184 mhz) 0.031 2.8 8 c16o- (16.384 mhz) 0.090 5.5 9 c19o (19.44 mhz) 0.038 2.0 dejittered with analog pll 10 c19o (19.44 mhz) 0.059 3.0 analog pll bypassed 11 c34o (34.368 mhz) 0.092 2.7 12 c44o (44.736 mhz) 0.110 2.5 13 c155o (155.52 mhz) 0.170 1.1 14 f0o (8 khz) na 4.7 15 f8o (8 khz) na 4.0 16 f16o (8 khz) na 3.1

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